1. Field of The Invention
The invention relates to a multi-position, binary parallel computing arrangement for additions or subtractions, with sequential carry propagation and with a clock circuit permitting a variable operating time.
2. Description of Prior Art
In parallel adders the clock time for processing two operands is a function of the time required for rippling carries, if any. Therefore, it is necessary to assume the worst case where a carry has to pass all positions of the computing arrangement. As this happens relatively rarely, a fixed clock time would lead to considerable idling.
It is known to shorten the operating time of binary adders by scanning the carry signals rippling from one digit position to another for the end of the carry processing step ("The Logic of Computer Arithmetic", pp. 79-81, by I. Flores, London 1963). Such an arrangement which is also referred to as carry-complete adder operates asynchronously. OR-circuits, connected to an AND-circuit common to all digit positions, are associated with the carry outputs of the individual digit positions. A carry signal appearing in one of the digit positions is transmitted to the common AND circuit via the OR circuit of the respective digit position. The arrangement is such that the carry signals are maintained until the end of an addition. Apart from this, each carry connection from one digit position to the next higher one consists of two lines, one of which carries the true signal, whereas the other carries the negated carry signal. At the beginning of an addition, both lines are without signals. After the operands have been fed to the adder and addition has begun, a certain signal state occurs within the carry connections as the carries are being handled. After this state has been reached for all digit positions of the adder, the common AND circuit emits an output signal indicating the end of addition. In this instance, the operation cycle is discontinued and transmission of the result from the result register to the connected units can be initiated.
This arrangement has the disadvantage of requiring extensive circuitry for generating the true and negated carry signals and for determining by scanning means whether these carry signals are present in their entirety. Furthermore, such an arrangement is intended for use in asynchronously operating processors which since they permit the end of a carry processing operation being detected at an early state, can utilize the advantage thus obtained by immediately initiating subsequent operations. An effective use of the known arrangement would necessitate, for example, that immediately after the carry rippling step is completed, the result is passed on or evaluated, irrespective of the switching state the processor is in at this stage. Processors organized in this way are not being used too widely because of the extensive circuitry they require. When processors are organized the emphasis is rather on synchronous operation, whereby fixed clock times are associated with the individual transmission and operation cycles.
On the other hand it is known to provide a varying number of machine cycles for specific operations in synchronously operating processors. This is done under the control of the operation code of those instructions that control the respective operations. The control signals derived from the operation code act on the clock circuit which is thus enabled to provide a variable number of machine cycles.